FIG. 1 shows a circuit arrangement based on the prior art, where a master circuit is connected to two slave circuits in a star shape. Unlike the master circuit, the slave circuits have no processor for executing a stored program. The data output of the master circuit (Dout) is connected to the data inputs (Din) of the slave circuit A, B by means of a first data bus. The data outputs of the slave circuit Slave A, Slave B are connected to the data input of the master circuit by means of a further data bus. The data lines can be a single data line for serial data transmission or a data bus for parallel data transmission. In the circuit arrangement shown in FIG. 1, the master uses a respective chip selection line (Chip Select) to select a slave circuit for data transmission. A slave circuit is selected by the master circuit using said slave circuit's associated selection line for the purpose of reading data or for writing data. Optionally, “pull up” resistors can be provided on the data lines routed to the data input Din of the master circuit. The pull up resistors provided on the data output lines of the slave circuits allow operation with open drain output drivers, which prevents damage when various slave circuits simultaneously transmit different data on a data line to the master circuit.
In the case of the circuit arrangement shown in FIG. 1, an independent chip select line is provided for each slave circuit Slave A, Slave B. In an alternative embodiment, the master circuit outputs an address signal via an address bus which is connected to a decoding circuit. The address bus transmits, by way of example, an 8 bit address from the master circuit to the decoding circuit, which sends 256(=28) different chip select signals therefrom to a maximum of 256 different slave circuits. Such a separate decoding circuit is also referred to as “glue logic”.
FIG. 2 shows a timing diagram for the data transmission in the case of a serially controlled interface (SCI) in the circuit arrangement shown in FIG. 1.
A drawback of the circuit arrangement shown in FIG. 1 is that an independent chip select line or an additional address decoding circuit needs to be provided for every slave circuit. In addition, pull up resistors are necessary for the data output lines from the slave circuits.
For this reason, the circuit arrangement shown in FIG. 3 has been proposed, which dispenses with the chip select selection lines for actuating the slave circuits Slave A, Slave B. In the circuit arrangement shown in FIG. 3, the data output of the master circuit is connected by means of a first data bus or a first data line to all the slave circuits Slave A, Slave B connected in a star shape. In the same way, the data outputs Dout of the slave circuits are connected to a data input (Din) on the master circuit by means of a further data bus or data line. In the circuit arrangement shown in FIG. 3, the data are transmitted to the master circuit and to the slave circuits using data frames. The data frames can be transmitted from the master circuit to the slave circuit using any desired data transmission protocol, for example the HDLC data transmission protocol. The data frames contain administration data or header data and user data or payload data. The administration data comprise an address data field which is used to address the slave circuits Slave A, Slave B. In the circuit arrangement shown in FIG. 3, each slave circuit is connected to an associated, generally hardwired (pin strapped) address register in which the address of the slave circuit is stored. The slave circuit takes the data processing protocol as a basis for extracting the slave address contained in the transmitted data frame and compares said slave address with the slave circuit's hail address hardwired in the address register. If the two addresses are identical, then the slave circuit accepts the user data contained in the data frame for further data processing.
FIG. 4 shows a timing diagram for the data transmission in the circuit arrangement shown in FIG. 3. The master circuit and the slave circuit are clocked by means of a common clock signal. The master circuit uses a flag byte, for example, to indicate the data transmission and selects the desired slave circuit using an address byte. The subsequent user data are processed by the selected slave circuit.
FIG. 5 shows the circuit design of a slave circuit in the circuit arrangement shown in FIG. 3. The slave circuit essentially comprises a data transmission interface for receiving and sending data frames and also an internal data processing unit for processing the user data transmitted in the data frames. The address of the slave circuit is stored in a generally hardwired address memory. Alternatively, the address memory can also be programmable.
The drawback of the slave circuit shown in FIG. 5 is that the slave circuit requires at least 3+N connection pins when it is integrated on a chip, namely one connection pin for the clock signal (CLK), at least one connection for a data input line, at least one connection for a data output line and N connection lines for connection to the hardwired address register, if the address comprises N bits. The relatively large number of connection pins or connection pads complicates the miniaturization and integration of the slave circuit based on the prior art which is shown in FIG. 5.